A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300°C

While state of the art sensor systems get more and more complex and highly integrated, high-temperature sensors often include a set of multiple discrete components like dedicated amplifiers or analog to digital converters, due to the lack of higher integrated chips. In addition, these are often rated to maximum operating temperatures of 210°C [1] or below. In the course of the Fraunhofer Lighthouse Project “eHarsh,” several technologies have been investigated to realize high-temperature sensor systems up to 300°C [2]. Research and development topics of this project are sensors, sensor electronics, packaging and accompanying material, and device characterization as well as test and reliability simulation and analysis. This article focuses on the integrated sensor electronics and gives an overview on the applied assembly technologies. The integrated sensor electronics is a set of three chips. The current development is dedicated to resistive, especially piezo resistive sensors, developed in the project as well [3].

The overall goal was to develop a modular high-temperature capable chipset with a minimum set of necessary components to realize the full sensor electronics. Besides the chips only blocking capacitors are necessary as external components. Therefore, the typical elements of a sensor electronic are distributed over three chips, i.e., a sensor-specific analog frontend chip, a Microcontroller, and finally a sensor interface chip. All chips are designed in a high-temperature 0.35-micron SOI-CMOS technology for a maximum target operating temperature of up to 300°C.

The analog frontend chip includes all functions to excite and readout resistive sensors. It includes three separate signal paths supporting simple resistive sensors as well as sensors in Wheatstone configuration. Each signal path is equipped with a programmable gain amplifier (PGA) with integrated input offset and sensor offset correction and a sigma delta converter (SDC) as depicted in Fig. 1.

Fig. 2 shows the top level of a single signal path. The input stage is built of a differential structure as common for an instrumentational amplifier. For canceling the amplifier input offset and suppression of flicker noise, the amplifiers are realized as auto-zero amplifiers. Additionally, the offset of a connected sensor bridge can be corrected internally. The gain of the amplifier is programmable to adapt the sensor bridge full-scale swing to the SDC input range. The summing amplifier is omitted and the signal is fed differentially into the subsequent SDC.

The sigma delta modulator is implemented in a three-stage topology as depicted in Fig. 3.

The modulator is built fully differential using switched-capacitor technique. The input stage uses correlated double sampling to reject any common mode signal from the input stage. The following two stages are realized in a standard integrator topology. The output is finally discretized by a clocked comparator.

For decimation of the digital bitstream, a fourth-order sinc-filter (sinc4) is used. The filter supports various decimation factors from 32 to 2048.

For signal processing and sensor control, a 32-bit micro-controller is in development. It is realized based on the RISC-V instruction set (RV32IMC) supporting integer multiplication and division as well as compressed instructions. The microcontroller is equipped with standard peripherals such as UART, SPI, I²C, and timers. In addition, it includes a 12-bit SAR ADC. For code storage, 16-Kbyte of high-density-EEPROM have been developed. Further, 4-Kbyte of RAM and a 512-byte EEPROM, e.g., to store calibration data are included. Debugging of the processor is supported via a JTAG interface. Fig. 4 shows the current block diagram of the overall controller.

The supply and interface chip includes voltage regulators to supply the microcontroller and the analog signal path, respectively. The chip supports input voltages from 4.5 to 6.5 V. As a reference, an internal bandgap is used. In addition, the chip is equipped with an RS485 interface intended as sensor bus interface.

Numerous analysis have been performed on the analog fron-tend and the interface chip. This article concentrates on the fron-tend chip results. The SDC has been characterized for DC- and AC-signals at different temperatures up to 250°C. Therefore, the analog to digital converter has been characterized with regard to dynamic figures such as signal-to-noise ratio (SNR), total harmonic distortion (THD), and signal-to-noise and distortion ratio (SNDR). An oversampling factor of 64 was chosen which corresponds to a sample frequency of 31,250 Sps. The results can be seen in Fig. 5. The SDC uses a reference voltage of 2.5 V. The simulated stable input range of the third-order SDC for sinusoidal signals is about ±50% of the reference voltage. Because of the double sampling used in the first stage, the input range is halved to −625 mV to 625 mV. In the measurement, the stable input range for DC signals is about −850 mV to 850 mV. The SNR extracted from the measurement results varies over temperature from 87 dB at 20°C to about 84 dB at 250°C.

Furthermore, the signal path, including the PGA and SDC, has been characterized for sine signals. Fig. 6 shows the power spectrum of the converter output to an 8-Hz sine signal at 250°C. The PGA was used in auto-zero mode with an amplification of 1.5. The sine signal amplitude was chosen to 420 mV, which is at the edge of the simulated stable input range. In the sinc4-filter, a decimation factor of 2,048 was used which corresponds to about 1 kSps output frequency.

To calculate SNR, THD, and SNDR, the frequencies below 0.5 Hz have been removed, because they are dominated by the window function which was used to minimize leakage in the Fourier transformation. The noise floor of the power spectrum is dominated by 1/f-noise. This leads to an SNR of 85 dB. The THD is −89 dB. There are some distortions related to the power supply at 50 Hz, multiples of 50 Hz and intermodulations between the 50 Hz and the 8 Hz signal frequency. The SNDR that also includes the power supply distortions is 80 dB. To further optimize the SNDR, a reduction of 1/f noise and lower distortions by the power supply are possible. This can be achieved by chopping of the first integrator stage in the SDC and by using an additional digital filter that removes the 50 Hz distortions.

Fig. 7 shows a chip photo of the realized frontend chip. Fig. 8 shows the chip photo of the supply and interface chip.

The features of the analog frontend chip and of the supply and interface chip are presented in Tables I and II.

The chipset has been designed based on the Fraunhofer IMS HT-SOI-CMOS technology H035 [4]. The technology allows the design of circuits for operating temperatures up to 300°C. Fig. 9 shows a cross section of the technology.

H035 is a partially depleted thin film SOI CMOS technology. Due to the thin silicon film thickness and the insulation oxide layer, leakage currents are reduced by about three decades at 250°C compared with bulk technologies, which allows mixed signal operation up to about 300°C. The technology features two different gate oxides (9.4 nm and 40 nm) with dedicated devices like digital and analog transistors, respectively.

The technology is equipped with four layers of tungsten metallization for reliable high-temperature operation without any electromigration issue.

As a nonvolatile memory, EEPROM cells are available which support standard EEPROM memory topologies. For larger memory arrays as typically used for code storage, a high-density variant has been realized.

Besides the development of the integrated sensor electronics, several complementing technologies have been investigated to build a highly reliable sensor. This chapter gives an outline on the realized ceramic board and the technology used for chip assembly.

To achieve a highly reliable system, a ceramic board is used as circuit carrier. The board is manufactured using ceramic multilayer technology, which is an established method for the manufacturing of microcircuits. The process (Fig. 10) uses ceramic green tapes, manufactured by tape casting, and functional pastes as semifinished products.

Initially, ceramic base materials are selected. The materials are synthesized, mixed and casted into ceramic tapes using a ceramic slurry. During the drying process, the solvent of the slurry evaporates and the dried tape is rolled into a coil. Compatible pastes will be selected forming the inner and outer layer and via hole metallization. During a blanking step, the ceramic tapes are cut into defined sizes (normally 4 × 4sqin upto 8 × 8 sqin) and are geometrically structured by punching (creation of via holes) or lasing. The via holes will afterward be filled by stencil printing of a metallization paste, followed by screen printing of a predefined conductor layout. The individual tapes will then be stacked, laminated, and sintered. During the pressureless/pressure-assisted sintering process, the laminated stack transforms into a monolithic ceramic body. If necessary, further materials can be deposited on the fired substrate (might be necessary due to the need of reduced temperature stability or material interaction issues). Finally, the multiple panel is singularized using laser technology, wafer sawing, or scratching/breaking.

Depending on the chosen sintering temperature, the involved materials can be divided into low-temperature cofired ceramics (LTCC), with sintering temperatures below 1,000°C, and high-temperature cofired ceramics (HTCC) with higher sintering temperatures. The process allows not only for the ceramic integration of conductive structures, but also for integrating resistive, highly capacitive, or magnetic structures. Hence, it is possible to transfer passive devices (R, L, C) into the ceramic substrate allowing for miniaturization. The integration of channels, cavities, and chambers is also possible.

The dielectric ceramic base material of the manufactured circuit board consists of a glass-ceramic composite with high temperature stability (Tg > 600°C), low CTE (6 ppm/K), high mechanical strength (320 MPa), and excellent isolation resistance (>10¹² Ω) even under higher temperatures. The circuit board is built up of four dielectric layers. The top layer bears the AgPt-based contact pads for the attachment of the integrated circuits and the passive components alternatively by wire bonding, flip chip silver sintering, or simply soldering. An additional soldering frame is provided for the hermetic integration of the electronic components under a cap of metallic Kovar material. Further, contact pads are positioned at the sides of the circuit board, alternatively manufactured in AgPt or Au for welding or wire bonding. Vias provide the electrical interlayer connection to the buried redistribution conductor lines. Vias consist of AgPd mixed metal materials and have a diameter of 0.2 mm. The redistribution conductor lines are fully embedded and manufactured using Ag pastes. The lower three dielectric layers provide the necessary stability for the handling of the circuit board. Fig. 11 shows a sketch of the ceramic circuit board layers.

In contrast to the classical assembly approach using die attach and wire bonding, a reliable high-temperature flip-chip technology has been investigated.

With regard to the maximum target operating temperature of up to 300°C it was evaluated if the silver sintering technology can be applied to generate reliable high-temperature flip-chip interconnects between the SOI-CMOS chips and the ceramic circuit board as depicted in Fig. 11.

It has already been shown that a significant increase in the lifetime can be reached by using silver sintering [5, 6]. However, up to now, this interconnection technology is solely used for die attach applications, especially in the field of power- or optoelectronics, when higher operating temperatures (>150°C) or generally optimized heat conductions are required. Depending on the application, the process parameters for die attach interconnects are already known or need to be optimized. Commercial silver sintering pastes are available and adjusted to the noble metallization systems commonly used in power- and optoelectronics, i.e., electroless Ni/Au (ENIG) and Ni/Pd/Au (ENEPIG) or immersion Ag. Typically, there are no critical requirements with regard to the dimensions and spacing of the die attach interconnects. Shortcuts can easily be prevented during the bonding process.

Using the silver sintering technology for flip chip bonding, new challenges have to be approached.

In case of the developed sensor system, a variety of fine-pitched electrical insulated connections per chip have to be bonded to a relatively uneven ceramic substrate.

Additionally, the thick film metallization of the substrate is rather rough and has added a certain amount of glass. Since the commercial silver sintering pastes are not specially tailored for this kind of metallization, it needs to be evaluated if it is even possible to generate a reliable bond between the sintered silver and the metallization of the ceramic circuit board.

As a first step to adjust the silver sintering process to the new approach it was tested how fine-pitched the silver sintering paste can be applied.

For the evaluation, a selection of commercial silver sintering pastes with μ-scaled silver particles were used. The pastes were applied by screen printing. The printing design was adapted to the design of the chipset and the conducting paths of the ceramic substrate with openings having each a diameter of 200 μm and a pitch of 400 μm. The stencil had a thickness of 50 μm. The printing tests were performed by using ceramic circuit boards with AgPt thick film metallization. Depending on the sintering paste used, it was possible to achieve reproducibly good printing results. This means that no bridging occurred between the single printed paste depots and only minor deviations of the paste bump heights (in relation to the stencil thickness) have been determined. Fig. 12 shows detailed microscope images of a substrate with the printed and dried silver paste depots as well as a detailed 3-D laser scan image of the printed conducting paths of the ceramic circuit board.

The average bump height was 55 μm. The subsequent pick and place process as well as the sintering step were conducted with a flip-chip bonder. The sintering was conducted by applying pressure of 30 MPa for 3 min. The sintering temperature was set to 230°C. All three chips (see Fig. 13) were sintered simultaneously. Using a bonder with a specialized gas chamber, this process can be conducted either in air or in a nitrogen-rich atmosphere.

Cross sectioning was conducted in order to evaluate the quality of the flip-chip interconnects.

The results show that high-quality interconnects can be generated for both the small chip variant with 40 electrically insulated connections per chip and the large chip variant with 76 electrically insulated connections per chip (see Fig. 14).

The microstructural analyses show (see Figs. 15 and 16) that by applying the selected process parameters, the residual porosity of the flip-chip bond is very low and that firmly bonded interconnections between the sintered silver layer and the AgPt thick film metallization can be generated.

In the course of the Fraunhofer Lighthouse Project “eHarsh,” a chipset for electronic readout of sensors including three chips, an analog frontend chip for resistive sensor readout, a microcontroller for signal processing and sensor control, as well as a combined supply and interface chip have been realized. For assembly, ceramic boards have been used in combination with flip-chip bonding. Reliable flip-chip connection based on silver sintering have been developed and successfully tested.

First measurement results of the sigma delta modulator show good performance up to 250°C. Further characterization of the chipset and reliability analysis of the whole system are ongoing.

The modular approach of the chipset allows to add further fron-tends dedicated to other sensor types. In addition, by combining some of the blocks, higher integrated systems are feasible.

This work was supported as a Fraunhofer Lighthouse Project.