Silver Sintering of Packaged GaN-Devices on Printed Circuit Board

The drive inverters for automotive applications are moving toward electrification including the trend from an internal combustion engine to plug-in-hybrid or pure electric vehicles [1]. Power electronics are at the core of these developments. Thereof the dominant trend for power electronics and power modules goes to higher efficiency, lower losses, and higher lifetime [2].

The highest power losses in power electronics modules are in the power devices, which are traditionally based on Si. In many applications, wide bandgap devices (WBG) are showing better performance and are more and more applied. These WBG devices, e.g., GaN offer lower switching and conduction losses as well as a higher power density compared with Si—depending on the case of usage. The use of GaN devices in power electronic converters in electric vehicles can improve their performance [3–5], leading to four times lower losses, four times smaller and lighter systems [6, 7] compared with Si-based power converters. Commercial GaN devices are preferably available as surface mount devices (SMDs) [3].

Reliability, lifetime, and thermal management are significant challenges for power modules in power converters for motor drive systems [8]. For sintered semiconductor joints, the lifetime and thermal conduction are higher, compared with soldered connections [9–11]. GaN SMD packages in power modules are soldered despite the advantages, as mentioned above, of silver sintering.

Reasons are the lower cost for soldering as well as process technological challenges for silver sintering.

Within the scope of this article, a silver sintering process for GaN SMDs on printed circuit board (PCB) was developed. Therefore, Finite Element Method (FEM) analysis and measurements were conducted. The results were incorporated in the silver sinter paste experiments with different paste systems.

A thermal comparison of the setup (sintered connection) with the reference (soldered connection) was carried out. Then, the stress distribution inside the package during sintering was analyzed with numerical methods. The pressure sensitivity of the GaN packages was furthermore analyzed. Different sintering paste variants were used to reach the aim of successfully sintering an electrical functional GaN package on PCB.

The respective methods, experiments, and sample testing are described in the following.

The PCB were designed and manufactured at HELLA. The design represented a compromise between application (e.g., implementation of thermal vias) and power cycling tests (single small PCB with only one transistor and connection pads for pressure contacts) for lifetime characterization. During sintering, the samples must resist high temperatures up to 250°C combined with pressure loading up to 20 MPa. Therefore, PCBs with high glass transition temperature T_g above 170°Cwere used. Those PCBs can withstand temperatures of up to 250°C for up to 3 min.

The GaN packages were high electron mobility transistors (HEMT) from GaN-Systems in SMD package with gold-plated contact pads on the bottom (Fig. 1). In the pressure sensitivity experiments on the GaN-HEMTs, the devices were soldered on the PCB. The soldering was done at HELLA.

For sintered joints, the thermal conductivity is higher compared with soldered joints [9, 10]. However, the difference in performance depends on the use case. A finite-element thermal steady-state simulation was conducted for this case where a GaN package is connected to a PCB via sintering respectively soldering. The software ANSYS Workbench 2019 R3 [12] was used. The model consisted of the prepackaged GaN device, an interconnection layer, and the PCB (Fig. 2), connected to an aluminum base plate via Thermal Interface Material (TIM). The geometry inside the GaN package was accurately reproduced and used for the steady-state simulation.

Three cases were considered for simulation: silver sintered interconnection layer with 93% density, soldered interconnection layer with 0% pore volume (ideal case), and soldered interconnection layer with 5% pore volume (realistic case).

The thicknesses of the modeled parts were as follows (Table I): Materials were assigned to each separate body reflecting the data from the datasheets. The isotropic thermal conductivity of the interconnection layer was 350 W/(m*K) at 25°C for the sintered case (bulk density of 93%) [13] and a value of around 57 W/(m*K) at 25°C for the soldered samples. For the PCB a value of .38 W/(m*K) was used for the FR4, for the Cu OFHC 401 W/(m*K) at 0°C respectively 388 W/(m*K) at 200°C and 1.18 W/(m*K) for the Epoxy (via fill). The thermal conductivity of the TIM was 5 W/(m*K) and for the Al heat sink 144 W/ (m*K) at 0°C respectively 175 W/(m*K) at 200°C.

A discretization in 940.000 finite elements with linear shape functions was performed. A higher element density was set for the areas of interest. The model was checked for mesh independence.

In the next step, the boundary conditions were applied:

1. heat transfer coefficient of 20,000 W/(m²*K) at a temperature of 30°C on the bottom of the heat sink top-plate to represent the cooling fluid

2. a convection boundary condition with a film coefficient of 5 W/(m²*K), an ambient temperature of 25°C on the free surfaces of the bodies

3. heat flux boundary condition with a magnitude of 48.5 W on the semiconductor surface inside the chip

The steady-state thermal model was run in the distributed mode using the sparse solver.

The second finite element analysis was done to study the chip damage during the sintering process. The dimensions and material properties were obtained from the previous thermal FE model.

The model (Fig. 3) was limited to two dimensions represented by plane stress conditions. Only a single time point, the last one of the sintering process, was analyzed with a homogenous temperature of 200°C for all bodies and no thermal strains were considered. A compression force was applied normal onto the top surface of the chip mold compound. Its magnitude was adjusted to reach 10 MPa pressure regarding the sinter layer contact area. The influence of the parameters porosity, thickness, and depth of the porous outer perimeter of the sintered layer (grad length) was analyzed. The term “porosity” in this case just relates to the area with lower density close to the edges of the sinter layer. The sinter layer has overall a remaining porosity but in the highlighted regions close to the edges, there is a higher amount of porosity due to the bending of the “unsupported” edges during sintering (away from the centric view of Fig. 3, there are supports for drain and source contacts).

The porosity influence was obtained via linear scaling of Young’s modulus and the yield function. A discretization in 121,000 finite elements with linear shape functions was performed.

The sensitivity of the GaN packages regarding applied pressure (e.g., during the sintering process) was examined. Therefore, soldered samples had to be used because there was no damage introduced during manufacturing.

The samples were mounted in a Lloyd Instruments universal mechanical testing device. An additional heating chamber was used for tests at elevated temperatures.

A force up to 500 N (equal to around 20 MPa on the contact surface) was applied. A swelling increasing force profile was used to determine the force were the devices fail (Fig. 8). After each hold time with constant force, a relaxation phase with the same hold time was used to be able to determine the reversible and irreversible changes in the electrical behavior. All experiments were carried out at different homogeneous environmental temperature up to 200°C.

In the first experiments, the gate leakage current was measured. During the second tests, the channel I–V characteristics were logged while the gate voltage was kept constant.

Different sintering process variants were analyzed in this article regarding their suitability for sintering the GaN package on PCB. The aims were to both obtain electrical working setups as well as an interconnection with a reasonable mechanical strength. In the following, the experiments for those processes will be described.

The whole process is conducted in a die placer.

First, the die transfer film (DTF) (Argomax® 8020) is cut out and attached to the die by placing it at a pressure of 2 MPa and 130°C onto the film. Then the die and the attached film are placed on the substrate. The sintering follows. During the process, axial pressure and temperature are applied. Details can be found in Mueller et al. [14].

The advantages of this process are a constant quality of the sinter material without defects as, e.g., voids. Furthermore, a subsequent sintering of semiconductors on preassembled PCBs is possible [14].

The substrates were precleaned via ArH₂ plasma. Pretests showed that the interface strength was thereby significantly increased when using a gold finish for the metal contacts. Next, the sintering paste Heraeus LTS 338 was applied to the contact pads of the package by jet-printing (Fig. 4) hence the final aim was an assembly on a prepopulated PCB. For this process, no extra tools are needed, and a selective application of the paste is possible. The method of jet-printing sintering paste is not used so far and currently is a topic of research. Details will be further described in future publications.

The paste was dried (120°C for 20 min), and the die was attached (1 s with 0.5 MPa at 130°C) to the PCB. Sintering in a uniaxial hot press Type Schmidt ServoPress 450 followed up. During the process, the temperature was kept constant at 260°C—according to the recommendations from the datasheet. The pressure was varied between 10 and 40 MPa and the sintering time was between 25 and 300 s.

For the first experiments, electrically nonfunctional packages were used. The aim was to optimize the shear strength. In the second step, electrically functional devices were used, and the channel I–V characteristics were measured after the sintering process.

Further samples were sintered, and metallographic cross-sections were made, to examine the inner structure of the package after sintering for defects.

Additional experiments with pressure-less sintering paste were conducted. However, an incomplete sintering of the link layer was observed. Thereof this method was not further examined.

The substrates also were precleaned via ArH2 plasma (to increase the interface strength, see previous point). First, the paste Alconano ANP-1 was stencil printed on the PCB with a thickness of 80 μm.

In preliminary tests, the paste was first dried according to datasheet followed by the die attach. Very weak attach of the die on the paste was observed. This was contributed to presintering of the paste. Furthermore, cracks were observed in the dried paste. The dice were attached to the wet paste using a die bonder, to resolve this problem. To identify the adequate pressure, Polymethyl-methacrylat (PMMA) dummy dice were used instead of the GaN-packages. Via the transparent samples an optical inspection of the paste depot was enabled. The dimensions of the dummies were the same as for the GaN packages. No deformation of the wet paste depot should occur to prevent short circuits.

Next, parameters for the drying process after the chip attachment were determined. The time was adjusted so that the paste reaches a state, where it is not visibly viscous. This was linked to a complete change in color of the paste. Furthermore, no drying cracks were observed.

The temperature for the sintering process was obtained from the datasheet. The time was set to a time of 300 s since previous sintering experiments have shown that a longer time resulted in higher shear strength. Furthermore, the time was kept constant to reduce the number of samples. The pressure was varied between 10 and 20 MPa hence the common pressure for pressure-assisted sintering varies between 10 and 30 MPa. Six samples were sintered for each parameter combination.

After each sintering experiment, the samples were analyzed concerning their shear strength to investigate the bonding quality. A Dage 4000 Plus was used for the shear tests. The samples were sheared perpendicular to the long side of the die at a height of 90 μm (thickness of sintering layer + 10% of sample thickness, according to MIL-STD-883 2019.9 [15]) until failure.

For closer examinations of the sintered layer and the inner structure of the GaN package after sintering, metallographic cross-sections were carried out. The samples were embedded in EpoThin with epoxy resin and sawed. The section plane passed through the die, inside the device package (see Fig. 3). The samples were grinded unto a granularity of 2,000 and polished. Light microscopic examinations of the samples followed.

The results in terms of temperature distribution in the global view (Fig. 5) show a maximum temperature difference of around 7°C between the sintered case and the solder case with 0% pore volume (not shown in the figure). The soldered case with 5% pore volume shows a much higher temperature difference to the sintered case (~14 K) given by the pores. These pores result in a reduced thermal conductivity for the solder layer. This shows the negative influence of pores in the maximum temperature. The Rth reflects this relation as well: for the soldered (5% pores), it is 2.89 respectively 2.61, for the sintered (93% density) case.

Previous sensitivity analyses had been carried out. Despite that different systems had been regarded, the parameters and variational ranges had been similar as the one in question. Those analyses had shown that the heat transfer coefficient of the interconnection layer has a much higher influence on the output temperature than its thickness.

This shows that a substantial thermal benefit can be earned by using sintering technology. In the next step, experiments for assembling the samples via sintering were carried out.

Only the contact pads of the package shall be covered (Fig. 1) by the DTF. The height difference between the protruding contact pads and the bottom of the package was only 20 μm for the used package. This pad height was too small to cause a cut-out of the desired structures, when pressing the package into the DTF. Instead, the whole bottom surface was covered, which is undesired. Using prestructured DTF was not examined due to process-technological difficulties.

A selective application of the sintering paste was therefore preferred in the further progress. Therefore, microscale sintering paste was printed selectively on the contact pads in the next steps. Jet-printing was used.

In the first experiments, the shear strength was optimized by varying the sintering parameters (Fig. 6).

An increase in both sintering time and sintering pressure resulted in higher shear strength. Shear strengths of ≥20 MPa were obtained for sintering times ≥225 s and a pressure of ≥20 MPa.

The measured channel I–V characteristics showed a significantly increased electrical resistance concluding electrical damage of the devices. The graphs will be presented later in this work (Fig. 12, Sinter V1).

Vertical cracks in the silicon substrate of the GaN device were observed (Fig. 7). These brittle fractures were starting in the top metallization of the GaN die and crossed the entire thickness to the back side. The width of the cracks was up to ~5 μm. These cracks caused the electrical failure.

For the first tests at room temperature (Fig. 8), a small change of the gate leakage current during the mechanical load change was observed. This can be contributed to the piezoelectric activity of GaN [16].

After restarting the test with the same sample, the same properties were obtained. Thus, no irreversible damage to this device property was observed even for 500 N mechanical load.

Since the samples in the previous sintering experiments had shown a significant increase of the forward resistance, the channel I–V characteristics were recorded during the following tests. Furthermore, the chamber temperature was increased to 150 and 200°C to include the thermal loading of the sintering process. Even at a temperature of 200°C, neither reversible nor irreversible changes in the channel I–V characteristics were observed.

No difference between the plots for different loads and temperatures was noted.

In summary, ambient temperature and pressure during the test were comparable to those during the sintering process. However, no electrical damage of the devices could be observed. Hence, the pressure is not solely responsible for the damage of the devices during sintering. Consequently, other parameters, which are, e.g., paste specific, have an influence. Therefore, they were considered in following as part of a numerical analysis.

The false-color graphics (Fig. 9) illustrate the first principal normal stress field in the area of the silicon substrate. The maximum occurs in the area where the semiconductor is in contact to the copper lead frame. Furthermore, high tensile stresses appear in the top surface of the die.

This tensile stress maximum was used as an evaluation criterion for further examinations. In these examinations, the influence of both porosity and thickness of the sintering layer on the maximum normal stress was analyzed.

According to the response surface (Fig. 10), the variation of the parameters results in a difference up to 35 MPa—for a sintering pressure of 10 MPa. A higher sintering pressure intensifies the relation.

Furthermore, the different parameters were relatively weighted to compare the strength of the influence (Fig. 11). The results show that the porosity has the highest influence followed by the thickness of the sintering layer and the length over which the porosity was varied (grad length).

In conclusion, reducing the sinter layer thickness, increasing the density, and reducing the gradient length over which the porosity varies results in less stress in the sintered die.

The results of the analysis indicated that the microstructure and geometry of the sintered layer influence the tensile stress in the setup and die.

The sinter paste, which was used for the previous experiments, contained microscale silver flakes. Since the micro-structure is determined by the particle size, a different paste variant with nanoscale silver particles was used subsequently.

The devices were electrically unaffected compared with soldered samples (Fig. 12, sinter final). No decrease in the drain current was observed. For a sintering pressure of ≥15 MPa, the average shear strength of ≥20 MPa was obtained (Fig. 13). The common failure mode was at the interface between the gold plating of the PCB and the silver sinter layer.

Soldered samples were assembled as a reference. Those samples showed no damage at all. The first sintered samples, where microscale sinter paste was used, were electrically damaged and showed cracks in the die.

Pressure sensitivity tests showed that the assemblies are not pressure sensitive for uniaxial pressure up to 20 MPa. Hence, the pressure is not solely responsible for the cracks during the sintering process. Numerical analysis pointed out, that the microstructure of the sintered layer influences the internal stresses. Using nanoscale sinter paste, electrically functional samples were produced, as mentioned above.

Compared with the microscale sinter paste, the nanoscale sinter paste reaches a high stiffness earlier in the sintering process. This high initial stiffness counteracts the chip substrate deflection from the applied sintering pressure. During sintering with microscale sinter paste, high stiffness is obtained after a longer time, and meanwhile, the pressure may cause irreversible damages in the silicon substrate. Hence, nanoscale sinter paste may help to compensate for such time-dependent phenomena when packaged chips are going to be sintered on PCBs.

The final sintering process was as follows: precleaning of PCB via ArH₂ plasma, stencil printing of Nihon Alconano® ANP-1 paste on the PCB at printing speed 100 mm/s and using a 60° blade without additional printing pressure, die placing on the wet paste at 0.4 MPa for 1 s, drying at 130°C on a hot plate and for 6.5 min, sintering at 240°C under air and with 15 MPa applied for 300 s.

Consequently, the feasibility of the sintering process of discrete GaN devices on organic circuit boards was proven.

A silver sintering process for discrete GaN devices on organic circuit boards has been developed. Thermal FE simulations have shown the thermal advantages of silver sinter joints as compared with solder joints even in this application.

The experiments showed that sintering via DTF was not possible for these packages. Using prestructured DTF was not examined due to process-technological difficulties. Sintering by jet-printed microscale sintering paste resulted in die cracks according to electrical measurements and cross-sections. Axial load tests showed that axial pressure up to 20 MPa does not damage the device in this assembly if the pressure is homogenously distributed. Structural numerical analysis depicted a relationship between the microstructure of the sintering layer and the tensile stress in the package and the die. Hence, the microstructure evolution influences the internal stress in the device. In the final sintering process, paste with nanoscale particles was used.

In the next step, a shear strength of 20 MPa at a sintering pressure of 15 MPa with electrical functional devices could be obtained by using nanoscale sinter paste.

This work received funding from the Federal Ministry of Education and Research as part of the project HELENE (support code: 16EMO0231).