Integrating more functionality into smaller size increases the heat dissipation density and emphasizes the need for thermal simulations and accurate thermal models. With a compact thermal model (CTM) the dynamic and steady state thermal behavior of a package with several heat dissipating dice can be modeled. The optimization of the model's parameters requires a properly defined cost function. In this paper a two-phase optimization routine was used to find simultaneously good capacitance and resistance values. The accuracy of the model was improved when effective surface areas defined the convections of a CTM. Parameter optimization in time domain, for variable thermal load and nonlinear system, was tested and found accurate, but time consuming.
Author notes
Kimmo Kaija received his M.Sc. degree in electrical engineering from the Tampere University of Technology, Tampere, Finland, in 2004, where he is currently pursuing his Ph.D. degree. His research interests include computational modeling of microelectronic systems.
Pekka Heino received the M.Sc. degree in technical physics from Tampere University of Technology, Finland, in 1994 and the Dr.Tech degree in computational engineering from the Helsinki University of Technology, Finland, in 1998. His research interests include macro- and microscale computational modeling of thermomechanical reliability of electrical interconnections, micro- and nanoscale heat transfer, and dynamic fracture in disordered systems.
Eero Ristolainen received the M.Sc. and Dr.Tech. degrees from the Helsinki University of Technology, Helsinki, Finland. In the 1980's and 1990's, he was a Postdoctoral Research Fellow, Michigan Technological University, Houghton, and a Professor (co-operating) with the University of Florida, Gainesville, respectively. In 1997, he joined the Department of Electronics, Tampere University of Technology, Tampere, Finland, where he is now a Professor of Microelectronics. His research interests have included IC-design, ultra high speed electronic circuits [SiGe/Si heterostructures (HBT's)], and silicon-on-insulator devices (SOI), RF IC-design, integrated analog-and mixed-circuits, integrated optoelectronics, modeling, electronic materials, and microelectronics packaging. He is the author or co-author of more than 100 papers and he is a frequent speaker (invited) at conferences all over the world.
