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Journal Articles

Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill

Ricky Tsun-Sheng Chou, John H. Lau, Gary Chang-Fu Chen, Jones Yu-Cheng Huang, Channing Cheng-Lin Yang ...

Journal of Microelectronics and Electronic Packaging (2022) 19 (1): 8–17.

https://doi.org/10.4071/imaps.1546248

Published: 07 April 2022

View article titled, Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill

Journal Articles

State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding

John H Lau

Journal of Microelectronics and Electronic Packaging (2022) 18 (4): 145–160.

https://doi.org/10.4071/imaps.1542066

Published: 04 January 2022

View article titled, State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding

Journal Articles

Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration

John H Lau, Cheng-Ta Ko, Chia-Yu Peng, Kai-Ming Yang, Tim Xia ...

Journal of Microelectronics and Electronic Packaging (2021) 18 (2): 29–39.

https://doi.org/10.4071/imaps.1419800

Published: 16 July 2021

View article titled, Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration

Journal Articles

Thermal Cycling Test and Simulation of Six-Side Molded Panel-Level Chip-Scale Packages (PLCSPs)

John H Lau, Cheng-Ta Ko, Chia-Yu Peng, Tzvy-Jang Tseng, Kai-Ming Yang ...

Journal of Microelectronics and Electronic Packaging (2021) 18 (2): 67–80.

https://doi.org/10.4071/imaps.1421341

Published: 16 July 2021

View article titled, Thermal Cycling Test and Simulation of Six-Side Molded Panel-Level Chip-Scale Packages (PLCSPs)

Journal Articles

Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers

John H. Lau, Cheng-Ta Ko, Tzvy-Jang Tseng, Chia-Yu Peng, Kai-Ming Yang ...

Journal of Microelectronics and Electronic Packaging (2020) 17 (4): 111–120.

https://doi.org/10.4071/imaps.1226533

Published: 15 December 2020

View article titled, Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers

Journal Articles

Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

John H. Lau, Cheng-Ta Ko, Chia-Yu Peng, Kai-Ming Yang, Tim Xia ...

Journal of Microelectronics and Electronic Packaging (2020) 17 (3): 89–98.

https://doi.org/10.4071/imaps.1137828

Published: 13 October 2020

View article titled, Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

Journal Articles

Recent Advances and Trends in Heterogeneous Integrations

John H. Lau

Journal of Microelectronics and Electronic Packaging (2019) 16 (2): 45–77.

https://doi.org/10.4071/imaps.780287

Published: 01 April 2019

View article titled, Recent Advances and Trends in Heterogeneous Integrations

Journal Articles

Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)

Heng-Chieh Chien, John H. Lau, Yu-Lin Chao, Ra-Min Tain, Ming-Ji Dai ...

Journal of Microelectronics and Electronic Packaging (2012) 9 (2): 97–103.

https://doi.org/10.4071/imaps.309

Published: 01 April 2012

View article titled, Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)

Journal Articles

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

Chien-Ying Wu, Shang-Chun Chen, Pei-Jer Tzeng, John H. Lau, Yi-Feng Hsu ...

Journal of Microelectronics and Electronic Packaging (2012) 9 (1): 31–36.

https://doi.org/10.4071/imaps.308

Published: 01 January 2012

View article titled, Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

Journal Articles

An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration

Shyh-Shyuan Sheu, Zhe-Hui Lin, Jui-Feng Hung, John H. Lau, Peng-Shu Chen ...

Journal of Microelectronics and Electronic Packaging (2011) 8 (4): 140–145.

https://doi.org/10.4071/imaps.307

Published: 01 October 2011

View article titled, An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration

Journal Articles

Design and Process of 3D MEMS System-in-Package (SiP)

John H. Lau

Journal of Microelectronics and Electronic Packaging (2010) 7 (1): 10–15.

https://doi.org/10.4071/1551-4897-7.1.10

Published: 01 January 2010

View article titled, Design and Process of 3D MEMS System-in-Package (SiP)

Journal Articles

Critical Issues of TSV and 3D IC Integration

John H. Lau

Journal of Microelectronics and Electronic Packaging (2010) 7 (1): 35–43.

https://doi.org/10.4071/1551-4897-7.1.35

Published: 01 January 2010

View article titled, Critical Issues of TSV and 3D IC Integration

NARROW

Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill

State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding

Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration

Thermal Cycling Test and Simulation of Six-Side Molded Panel-Level Chip-Scale Packages (PLCSPs)

Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers

Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

Recent Advances and Trends in Heterogeneous Integrations

Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration

Design and Process of 3D MEMS System-in-Package (SiP)

Critical Issues of TSV and 3D IC Integration

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